1. Field of the Invention
The present invention generally relates to memory address translation and more particularly to an improved method for translating two-dimensional cell coordinates of a memory to n-dimensional physical addresses.
2. Description of the Related Art
In the random access memory (RAM) test world, one of the most important tools for viewing and characterizing the test results of the Device Under Test (DUT) is a system that identifies the defective bits shipped from the tester (a.k.a “failmap”) in a buffer and displays the failmap on a monitor in a two-dimensional layout. Such a system is referred to herein as Real-Time-Display (RTD).
A real-time-display system, however, is expected to provide more than just displaying the (failed and non-failed) bits. It has to provide some visual cues about the location/identity of each and every bit that is investigated by the test person (hereafter referred to as “the user”), along with its buffer coordinate and physical address.
The buffer is regarded as a two-dimensional plane (although it is usually organized internally, in the test system, as a one-dimensional stream of bits) because the display, which is two-dimensional by nature, is considered to be a direct representation of the buffer contents. Therefore, a buffer coordinate is a set of two numbers (x, y), describing the bit's location in the buffer. Buffer coordinates give the user a general idea about the location of bits in the physical device under test (since the buffer layout attempts to be a one-to-one representation the DUT's physical layout), but what the user is really interested in is the physical address of a given bit.
A bit's physical address is most closely related to the bit's electrical address. That is, when accessing the bit from an external circuit, a row address and a column address are applied to the device under test's electrical pins and the bit's value is read from (or applied to, in the case of a memory write operation) one of a set of I/O pins. The row address, the column address and the I/O pin number define the bit's electrical address. The physical address is essentially the same thing as the electrical address, except that the physical address definition is more flexible. The bit's row is sometimes specified in terms of a row number or word-line. The bit's column—in terms of column number, column-select or bit-line. I/Os are also referred to as DQs. In addition, the user might be interested not only in these three attributes, but also a bank number, a segment number, a unit number, etc.
Since each device under test bit can be uniquely described by either a buffer coordinate or a physical address, each physical address corresponds to one and only one buffer coordinate—and vice versa. The process of deriving a physical address from a buffer coordinate is called “buffer to physical address translation” (hereafter referred to as simply “address translation”).
Every memory product has its own (usually unique) address translation scheme. Therefore, in order for a real-time-display system to provide physical addresses for a particular device under test, the real-time-display system has to know how to perform that device under test's address translation from the buffer coordinates (which are always known, by definition).
An immediate and straightforward approach to provide that information to the real-time-display system would be to use a lookup table (LUT) or an array of look up tables that describe address translation for the entire device under test. But this approach is impractical, since it requires and consumes huge amounts of memory in the real-time-display's system controller.
In an exemplary conventional solution to the address translation problem in real-time-display systems, the real-time-display programmer receives from the users (verbally or on paper or both) a description of the physical addresses layout of the device under test to be supported. The programmer then finds and/or creates a pattern, a function or an algorithm that can translate every buffer coordinate to its corresponding physical address for that particular device under test. Conventionally, there were very few cases in which one such algorithm could describe two or more different memory products.
The programmer then implements the algorithm in a computer language, such as “C” (the language in which the real-time-display system's software is written), compiles it, integrates it into the real-time-display software and tests the “new” program. The programmer then installs/updates copy of the new version on each real-time-display system that is going to be used for testing that particular device under test. The real-time-display systems, on which the updated version is installed, are now ready to report physical addresses. However, if an error (or a minor inaccuracy) in the address translation has been detected by the users, the process needs to be repeated.
The existing solution has the following drawbacks. First, the system's software needs to be upgraded for every new memory product. The users completely depend on the test system's programmer to support the new product. This makes turn around time substantially longer than if the users could simply apply their knowledge directly to the program. Every such “product support code” is rarely re-used for another product since there isn't a concept or a unified approach for describing the device under test, thus forcing the programmer to re-invent/re-think a description/algorithm for every new product. Thus, the programmer needs to learn and know at least the address translation aspect of each and every product to be supported on the real-time-display. Further, modifying the system's software source code, compiling and linking it can introduce bugs to the entire real-time-display system—not only the address translation part.
Using the exemplary conventional solution described above, almost every real-time-display system is unique in the sense that it supports a different collection of memory products. This poses a configuration management problem for the installed base of a large number of systems. The present invention overcomes these disadvantages, as discussed below.